1. Field of the Invention
The present invention relates to memory arrays and more particularly to latching and driver circuitry for use in reading data from static random access memory (SRAM) arrays. The invention may be implemented in BICMOS technology.
2. Description of the Related Art
The process of effectively reading a static random access memory cell normally requires several operations to be performed. For example, after a particular cell has been selected, a sensing operation must be performed to read the data in the cell. This typically requires a sense amplifier to sense a voltage differential across a pair of bit lines coupled to the cell. Next, it is often desired to activate a latch circuit to hold the data for further processing. This latch circuit is typically operated in synchronous fashion using a clock signal.
It is also frequently necessary to convert the data signal to a different voltage or current level in order to properly activate external logic circuitry. This is particularly important when the different stages of the data read-out circuitry are built with different transistor technologies. For example, sense amplifier circuits often use bipolar transistors and operate with a very small signal swing, whereas latch circuits and logic circuits operate at larger "ECL" (emitted-coupled logic) levels, or use FET transistors and operate at even higher "CMOS" or "BICMOS" levels.
A key design problem for most SRAMS is to provide an interface circuit between the small signal swing of a sense circuit output and the larger input signal swing normally required for the surrounding logic or driver circuits. Generally, the signal swing of the sense circuit is about a few hundred millivolts and the surrounding logic, if implemented in ECL technology, needs about 800 millivolts, or 2-3 volts if the surrounding logic is implemented in CMOS or BICMOS technology. While it is theoretically possible to have the sense amp drive to ECL levels, this is not a practical solution for most large SRAMS.
When the sense circuit must drive to CMOS or BICMOS levels, the required voltage gain is usually beyond the capability of ECL type circuits because of the saturation of the bipolar transistors. One solution has been to use a chain of CMOS inverters as an interface circuit. This, however, introduces significant delay.
A further attempt to improve performance is to use gated latches, such as given in Miyamoto U.S. Pat. No. 4,616,342 (FIG. 8), where the sense amp (29) drives a level shifter (51, 52) and a latch (28) through a pass gate (26', 27'); the latch then drives the main amplifier (29), whose output is signal DA.